The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including contact structures for contacting different tiers of a staircase fin stack containing vertically stacked transistors. The present application also relates to a method of forming such a semiconductor structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
Three dimensional (3D) monolithic integration is touted as an alternative for continued CMOS density scaling. By utilizing stacked transistors, a significant area reduction can be achieved. Also, shorter interconnect routing can be achieved utilizing shorter vertical wiring rather than longer horizontal wiring. Despite the above advantages in 3D monolithic integration, there remains a challenge in forming contact structures to such 3D stacked transistors that avoid requiring a large space.